1. Field of the Invention
The present invention relates to a method of fabricating a thin film transistor array substrate and a stacked thin film structure. More particularly, the present invention relates to a method of increasing the production yield of thin film transistor array substrate and stacked thin film structure.
2. Description of the Related Art
Great advances in multimedia communication come about with the breakthroughs in semiconductor fabrication and development in man-machine interfaces. Cathode ray tube (CRT) used to be the principle type of displays in the market because of its reliability and moderate pricing. However, in an environment with a multiple of desktop terminals/displays, the demand for environmentally friendly equipment is so acute that the bulky and power-zapping CRT no longer meets the demands of consumers. In the search for alternatives, thin film transistor liquid crystal displays (TFT LCD), which is light, radiation free and able to produce high-quality pictures at a low power rating have gradually become mainstream display products.
The display panel of most color thin film transistor liquid crystal displays mainly comprises a thin film transistor array substrate, a color filter array substrate and a liquid crystal layer. The thin film transistor array substrate includes an array of thin film transistors on a glass panel, a plurality of pixel electrodes that correspond to the thin film transistor and a plurality of scan lines and data lines. Each thin film transistor further comprises a gate, a channel, a drain and a source. The action of the liquid crystal molecules inside each pixel is controlled through these thin film transistors.
FIGS. 1A through 1C are schematic cross-sectional views showing the steps for forming a conventional thin film transistor array substrate. The method of forming a conventional thin film transistor array substrate includes the following steps. First, as shown in FIG. 1A, a substrate 100 is provided. A first metallic layer is formed over the substrate 100 and then the first metallic layer is patterned to form a gate 110 by performing photolithographic and etching processes, for example. Thereafter, a dielectric layer 120 and an amorphous silicon layer 130 are sequentially formed over the entire surface of the substrate 100. A second metallic layer is formed over the amorphous silicon layer 130. The second metallic layer is also patterned to form a source/drain 140 by performing photolitho-graphic and etching processes, for example. A passivation layer 150 is formed over the substrate 100 globally. Afterwards, a patterned photoresist layer 160 is formed over the passivation layer 150 above the source/drain 140.
As shown in FIG. 1B, using the patterned photoresist layer 160 as a mask, an isotropic etching of the passivation layer 150 is carried out to remove the passivation layer 150, the amorphous silicon layer 130 and the dielectric layer 120 exposed by the photoresist layer 160. However, in the process of etching the passivation layer 150, the amorphous silicon layer 130 and the dielectric layer 120, an etching solution with a higher etching rate on the amorphous silicon layer 130 than the dielectric layer 120 is often used. Since the exposed amorphous silicon layer 130 is completely removed before the dielectric layer 120, a portion of the amorphous silicon layer 130 on the sidewalls will be removed to form an undercut in an area labeled A.
As shown in FIG. 1C, a pixel electrode 170 is formed over the substrate 100. The pixel electrode 170 is electrically connected to the source/drain 140 through an opening in the passivation layer 150. Due to the presence of the undercut, the step coverage of the pixel electrode 170 above area A is often poor. Ultimately, this may lead to a premature break in the pixel electrode 170 and hence a failure of the pixel electrode 170 to register image signals. When breaks occur in the pixel electrode 170 frequently, the yield of thin film transistor array substrates will drop.